Integrated circuit with resurf region biasing under buried insulator layers

ABSTRACT

Complementary high-voltage bipolar transistors in silicon-on-insulator (SOl) integrated circuits is disclosed. In one disclosed embodiment, a collector region is formed in an epitaxial silicon layer disposed over a buried insulator layer. A base region and an emitter are disposed over the collector region. An n-type region is formed under the buried insulator layer (BOX) by implanting donor impurity through the active region of substrate and BOX into a p-substrate. Later in the process flow this n-type region is connected from the top by doped poly-silicon plug and is biased at Vcc. In this case it will deplete lateral portion of PNP collector region and hence, will increase its BV.

CROSS-REFERENCE TO RELATED APPLICATIONS

Under 35 U.S.C. §120, this continuation application claims benefits ofand priority to U.S. patent application Ser. No. 14/219,760 (TI-72037),filed on Mar. 19, 2014, the entirety of which are hereby incorporatedherein by reference.

FIELD OF THE DISCLOSURE

This disclosure is in the field of bipolar transistor fabrication, andis more specifically directed to the fabrication of transistors havingvarying characteristics on a common substrate according tosilicon-on-insulator (SOl) technology.

BACKGROUND OF THE DISCLOSURE

Integrated circuits have utilized bipolar junction transistors for manyyears, taking advantage of their high gain characteristics to satisfyhigh performance and high current drive needs. In particular, as is wellknown in the art, bipolar transistors are especially well-suited forhigh frequency applications, such as now used in wirelesscommunications.

Silicon-on-insulator (SOl) technology is also well-known in the art asproviding important advantages in high- frequency electronic devices. Asis fundamental in SOI technology, active devices such as transistors areformed in single-crystal silicon layers formed over an insulator layer,such as a layer of silicon dioxide commonly referred to as buried oxide(BOX). The buried oxide layer isolates the active devices from theunderlying substrate, effectively eliminating parasitic nonlinearjunction capacitances to the substrate and reducingcollector-to-substrate capacitances. To the extent that high frequencyperformance of bulk transistors was limited by substrate capacitance,SOl technology provides significant improvement.

In addition, SOl devices are robust in high voltage applications. Theburied oxide layer effectively eliminates any reasonable possibility ofjunction breakdown to the substrate.

However it has been observed that those transistor features thatfacilitate high frequency performance tend to weaken the device from ahigh bias voltage standpoint, and vice versa. This tradeoff hastypically been addressed by separately manufacturing high voltageintegrated circuits and high performance integrated circuits, with eachintegrated circuit having transistors optimized for their particularimplementation. This is because the process complexity resulting fromintegrating both high voltage and high performance devices in the sameSOl integrated circuit adds significant cost and exerts manufacturingyield pressure.

A conventional SOl bipolar transistor is designed to be a highperformance device. However, a high performance transistor is somewhatlimited by its construction, from a standpoint of both breakdown voltageand performance. As is fundamental in the art, the collector emitterbreakdown voltage (BVCEO) depends upon the thickness of collector regionand upon the doping concentration of the collector region. Lighterdoping of the collector region and a thicker collector region wouldincrease this breakdown voltage.

In a real circuit, the emitter and base of a PNP is biased around thehighest potential Vcc (relative to grounded substrate) while thecollector is switched between Vcc and 0. High B-C bias corresponds tozero potential at collector. At this condition grounded p-substrate doesnot deplete lateral portion of collector region and, hence, does nothelp to increase BV.

The emitter and base of an NPN is biased around the lowest potential GND(relative to grounded substrate) while the collector is switched betweenVcc and 0. High B-C bias corresponds to VCC potential at collector. Atthis condition grounded p-substrate depletes lateral portion ofcollector region and, hence, helps to increase BV.

What is needed is a method of increasing PNP BV without decreasingcollector doping concentration or increasing collector region thicknessof the PNP while including a high voltage NPN on the samecircuit/substrate.

SUMMARY OF THE DISCLOSURE

The following presents a simplified summary in order to provide a basicunderstanding of one or more aspects of the disclosure. This summary isnot an extensive overview of the disclosure, and is neither intended toidentify key or critical elements of the disclosure, nor to delineatethe scope thereof. Rather, the primary purpose of the summary is topresent some concepts of the disclosure in a simplified form as aprelude to a more detailed description that is presented later.

In accordance with an embodiment of the present application, anintegrated circuit structure including both NPN and PNP high voltagetransistors, the integrated circuit structure including both NPN and PNPhigh voltage transistors comprising: complementary PNP and NPNstructures; wherein the PNP and NPN structures include an SOIsemiconductor structure comprising: an p-type region; active PNP and NPNdevice regions; a buried insulator layer BOX that lies therebetween,touches, and electrically isolates p-type region from the active PNP andNPN regions; wherein both the p-type region and the active device PNPand NPN regions are implemented with single-crystal silicon; and ann-type region is included under the buried insulator layer BOX of thePNP transistor, by implanting donor impurities of through the activedevice region of the SOI wafer and BOX into the p-type region.

In accordance with another embodiment of the present application, anintegrated circuit structure including both NPN and PNP high voltagetransistors, the integrated circuit structure including both NPN and PNPhigh voltage transistors comprising: complementary PNP and NPNstructures; wherein the PNP and NPN structures include an SOIsemiconductor structure comprising: an n-type region; active PNP and NPNdevice regions; a buried insulator layer BOX that lies therebetween,touches, and electrically isolates the n-type region from the active PNPand NPN device regions; wherein both the n-type region and the activePNP and NPN device regions are implemented with single-crystal silicon;an n-type region is included under the buried insulator layer BOX of thePNP transistor, by implanting donor atoms through the active deviceregion of the SOI wafer and BOX into the n-type region; a p-type regionis included under the buried insulator layer BOX of the NPN transistor,by implanting accepter impurities through the active device region ofthe SOI wafer and BOX into n-type region

DESCRIPTION OF THE VIEWS OF THE DRAWING

FIG. 1 illustrates a cross-section of an embodiment of the presentdisclosure.

FIG. 1A illustrates an enlarged portion of FIG. 1 detailing the NPNtransistor.

FIG. 1B illustrates an enlarged portion of FIG. 1 detailing the PNPtransistor.

FIG. 2 illustrates a cross-section of another embodiment of the presentdisclosure.

FIG. 2A illustrates an enlarged portion of FIG. 2 detailing the NPNtransistor.

FIG. 2B illustrates an enlarged portion of FIG. 2 detailing the PNPtransistor.

FIG. 3 illustrates the calculated dependencies of BV_(CER) on structureswith no resurf and structures including resurf.

In the drawings, like reference numerals are sometimes used to designatelike structural elements. It should also be appreciated that thedepictions in the figures are diagrammatic and not to scale.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

The present disclosure is described with reference to the attachedfigures. The figures are not drawn to scale and they are provided merelyto illustrate the disclosure. Several aspects of the disclosure aredescribed below with reference to example applications for illustration.It should be understood that numerous specific details, relationships,and methods are set forth to provide an understanding of the disclosure.One skilled in the relevant art, however, will readily recognize thatthe disclosure can be practiced without one or more of the specificdetails or with other methods. In other instances, well-known structuresor operations are not shown in detail to avoid obscuring the disclosure.The present disclosure is not limited by the illustrated ordering ofacts or events, as some acts may occur in different orders and/orconcurrently with other acts or events. Furthermore, not all illustratedacts or events are required to implement a methodology in accordancewith the present disclosure.

In an embodiment of the present disclosure is shown in FIGS. 1-1B, thecomplementary PNP 100 and NPN 200 structures include an SOIsemiconductor structure having an p-type region 101, active deviceregions 104 and 204 respectively, and a buried insulator layer (BOX) 103that lies therebetween, touches, and electrically isolates p-type region101 from the active device regions 104 and 204. The initial doping levelof the active device regions 104 and 204 can be n-type, ˜1e14 1/cm3. Inthe present example, both the p-type region 101 and the active deviceregions 104 and 204 are implemented with single-crystal silicon. Tocreate a structure that has higher PNP BV, an n-type region 106 isincluded under the buried insulator layer (BOX) of the PNP transistor100, by implanting donor impurities with dose of about 1e13 to 1e141/cm2 through the active device region of the SOI wafer and BOX 103(1.5-2 um in total) into p-type region 101. Later in the process flowthis n-type region 106 and the p-type regions 101 are connected from thetop by doped poly-silicon plugs and are biased at Vcc and GNDrespectively. Since the substrate is p-type material, GND can be appliedto either the p-type region 101 or the top contact GND. In this case itwill deplete lateral portions of both the PNP and NPN collector regionsand hence, will increase their BVs.

The structure providing a PNP transistor 100 with a higher BV (FIG. 1B)is described below.

First an SOI wafer is provided as described in the present disclosure asshown in FIGS. 1-1B.

Next, a first masking and implant step is accomplished to create ahighly (˜1e17 1/cm3) doped n-layer 106 under BOX 103 in PNP area. Thehighly doped n-layer 106 is vertically under the PNP area and extendstoward an n-type poly-silicon plug 110 and couples to that plug.

A second masking and implant step after Pad Oxidation, before Nitridedeposition is performed to create a uniform collector doping between3e14-3e16 in active device region 104.

A Third masking and etching step is accomplished to provide a hard maskfor defining and for deposition of an insulator layer STI 105 in theactive device region 104.

Deep trenches 109 are formed to encircle the PNP transistor 100 and then-type poly-silicon plug 110. The trenches extend from the top of thedie to the bottom of the BOX 103 and the n-type poly-silicon plugextends from the top of the die to and through the BOX 103 extendinginto the highly doped p-layer 106 under the BOX 103, wherein the n-typepoly-silicon plug touches the implanted n-layer under the BOX 103 andextends to the top of die providing a top contact to the implantedn-layer.

A base epitaxial semiconductor layer 113 is deposited, defined and dopedwith an impurity of the opposite conductivity type on top of the activedevice region 104 with base contacts 111 coupled thereto.

And finally, an emitter region 108 covers a portion of the baseepitaxial semiconductor layer 113, wherein the emitter region 108 ishighly doped with the same conductivity type as the active device region104.

The structure providing an NPN transistor 200 with a high BV FIG. 1A isdescribed below.

First an SOI wafer is provided as described in the present disclosure asshown in FIGS. 1-1B.

A first masking and implant step after Pad Oxidation, before Nitridedeposition is performed to create a uniform collector doping between3e14-3e16 1/cm3 in active device region 204.

A second masking and etching step is accomplished to provide a hard maskfor defining and to for deposition of an insulator layer STI 105 in theactive device region 204.

Deep trenches 109 are formed, to encircle the NPN 200 transistor and thep-type poly-silicon plug 210. The trenches extend from the top of thedie to the bottom of the BOX 103 and the p-type poly-silicon plugextends from the top of the die to and through the BOX 103 extendinginto the p-layer 101 under the BOX 103, wherein the p-type poly-siliconplug touches the p-layer under the BOX 103 and extends to the top of dieproviding a top contact to the p-layer 101.

A base epitaxial semiconductor layer 213 is deposited, defined and dopedwith an impurity of the opposite conductivity type on top of the activedevice region 204 with base contacts 211 coupled thereto.

And finally an emitter region 208 covers a portion of the base epitaxialsemiconductor layer 213, wherein the emitter region 208 is highly dopedwith the same conductivity type as the first epitaxial layer 204.

The base epitaxial semiconductor for the NPN and the PNP can be eitherSiGe or silicon. The base epitaxial semiconductor can also be depositedin two operations, one for the NPN and one for the PNP.

In another embodiment of the present disclosure is shown in FIGS. 2-2B,the complementary PNP 300 and NPN 400 structures include an SOIsemiconductor structure having an n-type region 301, active deviceregions 104 and 204 respectively, and a buried insulator layer (BOX) 103that lies between, touches, and electrically isolates n-type region 301from the active device regions 104 and 204. The initial doping level ofthe active device regions 104 and 204 can be n-type, ˜1e14 1/cm3. In thepresent example, both the n-type region 301 and the active deviceregions 104 and 204 are implemented with single-crystal silicon. Tocreate a structure that has higher PNP BV, an n-type region 106 isincluded under a buried insulator layer (BOX) 103 of the PNP 300transistor, by implanting donor impurity of about 2e15 to 1e17 throughthe active device region of the SOI wafer and BOX 103 (1.5-2 um intotal) into n-type region 301. In addition, a structure that yieldshigher NPN 400 BV, includes p-type region 406 under the buried insulatorlayer (BOX) 103 of the NPN transistor, by implanting accepter impuritiesof about 2e15 to 1e17 through the active device region 204 of the SOIwafer and BOX 103 (1.5-2 um in total) into n-type region 301. Later inthe process flow, the n-type region 106 and the p-type regions 406 areconnected from the top by doped poly-silicon plugs and are biased at Vccand GND respectively. Since the substrate is n-type material, Vcc can beapplied to either the n-type region 301 or the top contact Vcc. In thiscase it will deplete lateral portions of both the PNP and NPN collectorregions and hence, will increase their BVs.

The structure providing a PNP transistor 300 with a higher BV FIG. 2B isdescribed below.

First an SOI wafer is provided as described in the present disclosure asshown in FIGS. 2-2B.

Next, a first masking and implant step is accomplished to create ahighly (˜1e17 1/cm3) doped n-layer 106 under BOX 103 in PNP area. Thehighly doped n-layer 106 is vertically under the PNP area and extendstoward an n-type poly-silicon plug 110 and couples to that plug.

A second new masking and implant step after Pad Oxidation, beforeNitride deposition is performed to create a uniform collector dopingbetween 3e14-3e16 in active device region 104.

A Third masking and etching step is accomplished to provide a hard maskfor defining and to for deposition of a shallow trench insulation layerSTI 105 in the active device region 104.

Deep trenches 109 are formed to encircle the PNP transistor 300 and then-type poly-silicon plug 110. The trenches extend from the top of thedie to the bottom of the BOX 103 and the n-type poly-silicon plug 110extends from the top of the die to and through the BOX 103 extendinginto the highly doped n-layer 106 under the BOX 103, wherein the n-typepoly-silicon plug 110 touches the implanted n-layer under the BOX 103and extends to the top of die providing a top contact to the implantedn-layer 106.

A base epitaxial semiconductor layer 113 is deposited, defined and dopedwith an impurity of the opposite conductivity type on top of the activedevice region 104 with a base contact 111 coupled thereto.

And finally an emitter region 108 covers a portion of the base epitaxialsemiconductor layer 113, wherein the emitter region 108 is highly dopedwith the same conductivity type as the first epitaxial layer 104.

The structure providing an NPN transistor 400 with a high BV FIG. 1B isdescribed below.

First an SOI wafer is provided as described in the present disclosure asshown in FIGS. 2-2B.

Next, a first masking and implant step is accomplished to create ahighly (˜1e17 1/cm3) doped p-layer 406 under BOX 103 in NPN area. Thehighly doped p-layer 106 is vertically under the NPN area and extendstoward a p-type poly-silicon plug 210 and couples to that plug.

A second new masking and implant step after Pad Oxidation, beforeNitride deposition is performed to create a uniform collector dopingbetween 3e14-3e16 1/cm3 in active device region 204.

A Third masking and etching step is accomplished to provide a hard maskfor defining and to for deposition of an insulator layer STI 105 in theactive device region 204.

Deep trenches 109 are formed, to encircle the NPN 400 transistor and thep-type poly-silicon plug 210. The trenches extend from the top of thedie to the bottom of the BOX 103 and the p-type poly-silicon plug 210extends from the top of the die to and through the BOX 103 extendinginto the highly doped p-layer 406 under the BOX 103, wherein the p-typepoly-silicon plug 210 touches the implanted p-layer 406 under the BOX103 and extends to the top of die providing a top contact to theimplanted p-layer 406.

A base epitaxial semiconductor layer 213 is deposited, defined and dopedwith an impurity of the opposite conductivity type on top of the activedevice region 204 with base contacts 211 coupled thereto.

And finally an emitter region 208 covers a portion of the base epitaxialsemiconductor layer 213, wherein the emitter region 208 is highly dopedwith the same conductivity type as the first epitaxial layer 204.

The base epitaxial semiconductor for the NPN and the PNP can be eitherSiGe or silicon. The base epitaxial semiconductor can also be depositedin two operations, one for the NPN and one for the PNP.

FIG. 3 shows the dependencies of BV_(CER) f_(T) on the resurf n-layer.Calculated dependences of BV_(CER) (solid lines) and f_(T)peak atV_(CE)=10V (dashed lines) for PNP with lateral collector with (diamonds)and without (triangles) resurf N-layer. Note that without N-region, PNPBV saturates at ˜38V while with N-region it goes beyond 100V.

While various embodiments of the present disclosure have been describedabove, it should be understood that they have been presented by way ofexample only and not limitation. Numerous changes to the disclosedembodiments can be made in accordance with the disclosure herein withoutdeparting from the spirit or scope of the disclosure. Thus, the breadthand scope of the present disclosure should not be limited by any of theabove described embodiments. Rather, the scope of the disclosure shouldbe defined in accordance with the following claims and theirequivalents.

What is claimed is:
 1. An integrated circuit, comprising: asemiconductor substrate having a surface; a first region along thesurface, the first region having a first conductivity type; an insulatorlayer under the first region; a second region under the insulator layer,the second region having a second conductivity type opposite to thefirst conductivity type; and a conductive path having a first endextending from the surface, and a second end extending below theinsulator layer and reaching the second region.
 2. The integratedcircuit of claim 1, further comprising: a trench structure extendingfrom the surface and reaching the insulator layer, the trench structureinsulating the first region from the conductive path.
 3. The integratedcircuit of claim 1, further comprising: a trench structure extendingfrom the surface and reaching the insulator layer, the trench structureencircling the first region.
 4. The integrated circuit of claim 1,further comprising: first and second trench structures, each extendingfrom the surface and reaching the insulator layer, wherein theconductive path positioned between the first and second trenchstructures and has a greater depth than each one of the first and secondtrench structures.
 5. The integrated circuit of claim 1, wherein: thefirst conductivity type includes a p-type; the second conductivity typeincludes an n-type; and the conductive path includes an n-typepoly-silicon plug.
 6. The integrated circuit of claim 1, wherein: thefirst conductivity type includes an n-type; the second conductivity typeincludes a p-type; and the conductive path includes a p-typepoly-silicon plug and a p-type contact region interfacing the second endwith the second region.
 7. The integrated circuit of claim 1, wherein:the semiconductor substrate has the first conductivity type; and thesecond region includes a buried doped region having the secondconductivity type.
 8. The integrated circuit of claim 1, wherein: thesemiconductor substrate has the second conductivity type; and the secondregion includes a buried doped region having a higher dopingconcentration than the semiconductor substrate.
 9. The integratedcircuit of claim 1, wherein: the semiconductor substrate has the secondconductivity type; and the second region includes a same dopingconcentration as the semiconductor substrate.
 10. The integrated circuitof claim 1, further comprising: a bipolar transistor having: a collectorlayer in the first region, the collector layer having the firstconductivity type; a base layer above the collector layer, the baselayer having the second conductivity type; and an emitter layer abovethe base layer, the emitter layer having the first conductivity type.11. An integrated circuit, comprising: a semiconductor substrate havinga surface; a bipolar transistor having collector region under and nearthe surface, the collector region having a first conductivity type; aninsulator layer directly under the collector region; a doped regionunder the insulator layer, the doped region having a second conductivitytype opposite to the first conductivity type; a conductive path having afirst end extending from the surface, and a second end extending belowthe insulator layer and reaching the doped region; and a trenchstructure extending from the surface and reaching the insulator layer,the trench structure encircling the collector region and insulating thecollector region from the conductive path.
 12. The integrated circuit ofclaim 11, wherein: the first conductivity type includes a p-type; thesecond conductivity type includes an n-type; and the conductive pathincludes an n-type poly-silicon plug.
 13. The integrated circuit ofclaim 12, further comprising: a first terminal configured to receive afirst voltage supply (GND); a second terminal configured to receive asecond voltage supply (VCC) higher than the first voltage supply (GND),the second terminal coupled to the n-type poly-silicon plug.
 14. Theintegrated circuit of claim 11, wherein: the first conductivity typeincludes an n-type; the second conductivity type includes a p-type; andthe conductive path includes a p-type poly-silicon plug and a p-typecontact region interfacing the second end with the doped region.
 15. Theintegrated circuit of claim 14, further comprising: a first terminalconfigured to receive a first voltage supply (VCC); a second terminalconfigured to receive a second voltage supply (GND) lower than the firstvoltage supply (VCC), the second terminal coupled to the p-typepoly-silicon plug.
 16. The integrated circuit of claim 11, wherein: thesemiconductor substrate has a first doping concentration; and the dopedregion has a second doping concentration higher than the first dopingconcentration.
 17. An integrated circuit, comprising: a semiconductorsubstrate having a surface; a first transistor having a first p-typeregion under and near the surface; a second transistor having a firstn-type region under and near the surface; an insulator layer directlyunder the first p-type region and the first n-type region; a secondn-type region under the insulator layer and overlapping the first p-typeregion; a second p-type region under the insulator layer and overlappingthe first n-type region; an n-type poly-silicon plug extending from thesurface and penetrating the insulator layer to reach the second n-typeregion; and a p-type poly-silicon plug extending from the surface andpenetrating the insulator layer to reach the second p-type region. 18.The integrated circuit of claim 17, further comprising: a first trenchstructure extending from the surface and reaching the insulator layer,the first trench structure positioned between the first p-type regionand the n-type poly-silicon plug; and a second trench structureextending from the surface and reaching the insulator layer, the secondtrench structure positioned between the first n-type region and thep-type poly-silicon plug.
 19. The integrated circuit of claim 17,further comprising: a first trench structure extending from the surfaceand reaching the insulator layer, the first trench structure separatelyencircling the first p-type region and the n-type poly-silicon plug; anda second trench structure extending from the surface and reaching theinsulator layer, the second trench structure separately encircling thefirst n-type region and the p-type poly-silicon plug.
 20. The integratedcircuit of claim 17, further comprising: a first terminal configured toreceive a first voltage supply (VCC), the first terminal coupled to then-type poly-silicon plug; a second terminal configured to receive asecond voltage supply (GND) lower than the first voltage supply (VCC),the second terminal coupled to the p-type poly-silicon plug.